clash-verilog - Verilog backend for the CλaSH compiler
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CλaSH - A functional hardware description language
CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of CλaSH:
Strongly typed (like VHDL), yet with a very high degree of type inference,
enabling both safe and fast prototying using consise descriptions (like
Verilog).
Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are
fully parametric by default.
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.
Support for multiple clock domains, with type safe clock domain crossing.
