hsverilog

Synthesizable Verilog DSL supporting for multiple clock and reset

Latest on Hackage:0.1.0

This package is not currently in any snapshots. If you're interested in using it, we recommend adding it to Stackage Nightly. Doing so will make builds more reliable, and allow stackage.org to host generated Haddocks.

BSD-3-Clause licensed by Junji Hashimoto
Maintained by [email protected]

Synthesizable Verilog DSL supporting for multiple clock and reset